Test schedules for VLSI circuits having built-in test hardware
نویسندگان
چکیده
منابع مشابه
Test Scheduling and Control for VLSI Built-In Self-Test
The problem of exploiting parallelism in the testing of VLSI circuits with built-in self-test (BIST) was first introduced in [l]. In this paper, this problem is examined in detail using a broader modeling foundation and new algorithms. A hierarchical model for VLSI circuit testing is introduced. The test resource sharing model from [l] is employed to exploit the potential parallelism. Based on ...
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ژورنال
عنوان ژورنال: Computers & Mathematics with Applications
سال: 1987
ISSN: 0898-1221
DOI: 10.1016/0898-1221(87)90080-0